Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems

In sub-100nm technologies, leakage related problems are based on the standby current´s exponential dependency on both, parameter scaling and parameter variation. Countermeasures, reducing the standby current and its spread can be classified into 3 categories: First, improved devices can reduce leakage sources by orders of magnitude, requiring completely new process steps. Next, performance and leakage can be traded off for conventional technologies. Low leakage devices control standby currents but their performance loss will reduce applicability. Finally, power management implements and controls circuits, where leakage and performance can be tuned at run-time, saving power on idle. This part of the special session will focus on design of new devices, reducing the negative dependence on channel length, oxide thickness, and body potential and improving the switching behavior. Afterwards, device and circuit level techniques tackling drawbacks of popular power management techniques are presented. For power gating, this means a reduction of the recovery current, a circuit style having a predictable timing and low area overhead, and a design stabilizing the interface towards ungated parts. For body biasing, body currents dominating reverse bias and even influencing forward bias have to be regarded and controlled. The gain of state assignment techniques, which are easy to use with conventional EDA tools, needs to be boosted to justify their application.