Analysis of signal and power/ground pin assignment in multi-layer PCB and its impact on signal integrity and crosstalk

Author

Ka Fai Chang ; Cubillo, Joseph Romen ; Weerasekera, Roshan ; Cheng Jin ; Boyu Zheng ; Bhattacharya, Suryanarayana Shivakumar

Author_Institution

Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore

fYear

2013

fDate

11-13 Dec. 2013

Firstpage

789

Lastpage

792

Abstract

In this paper, the impact of signal and power/ground pin assignment in multi-layer printed circuit board (PCB) on signal integrity (SI) performance is studied. Efficient return signal current path plays an important role to preserve SI and minimize unwanted crosstalk. Moreover, a high pin count ratio of signal to power/ground is desirable to increase overall system throughput without trading off SI performance. A case study of a 4-layer organic substrate design is demonstrated for SI and power integrity verification. An optimum pattern of signal and power/ground pins in a regular tile pattern is populated over the floorplan to reduce timing skew (2 times improvement) and suppress crosstalk.

Keywords

crosstalk; electronics packaging; printed circuits; 4-layer organic substrate design; SI performance; high pin count ratio; multilayer PCB; multilayer printed circuit board; power integrity verification; power-ground pin assignment; regular tile pattern; return signal current path; signal integrity analysis; unwanted crosstalk minimization; Crosstalk; Layout; Pins; Silicon; Substrates; Tiles; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC 2013), 2013 IEEE 15th

Conference_Location

Singapore

Print_ISBN

978-1-4799-2832-3

Type

conf

DOI

10.1109/EPTC.2013.6745829

Filename

6745829