Title :
SPRAM (SPin-transfer torque RAM) design and its impact on digital systems
Author :
Kawahara, T. ; Takemura, R. ; Takahashi, H. ; Ohno, H.
Author_Institution :
Hitachi Ltd., Kokubunji
Abstract :
To demonstrate circuit technologies for potential low-power non-volatile RAM, or universal memory, we fabricated a 1.8V 2-Mb SPRAM (SPin-transfer torque RAM) chip using a 0.2-¿m logic process with a MgO tunneling barrier cell. This chip features an array scheme with bit-by-bit bidirectional current writing to enable proper spin-transfer torque writing and parallel-direction current reading for preventing read disturbance. In addition, this memory can improve the power efficiency of digital equipment.
Keywords :
logic design; low-power electronics; random-access storage; tunnelling; SPRAM; digital system; logic process; low-power non-volatile memory; size 0.2 mum; spin-transfer torque RAM; storage capacity 2 Mbit; tunneling barrier cell; voltage 1.8 V; Circuits; Digital systems; Laboratories; Magnetic devices; Magnetic memory; Magnetization; Random access memory; Read-write memory; Torque; Writing;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4511164
