Design and simulation of Fractional-N PLL frequency synthesizers

A fast simulation environment has been developed using MATLABM™ and CMEX™ for behavioral level simulation of Delta-Sigma (ΔΣ) based Fractional-N PLL frequency synthesizers. The simulator uses a differential equation approach with a uniform time step. To support a uniform time step in the simulation, the continuous-time average current-to-voltage loop filter transfer function is modeled as a discrete-time charge difference-to-voltage transfer function. Simulation results are presented on a type-II fourth-order PLL frequency synthesizer employing a third-order MASH ΔΣ modulator.