Title :
Automatic insertion of selective TMR for SEU mitigation
Author :
Ruano, O. ; Reviriego, P. ; Maestro, J.A.
Author_Institution :
Univerdad Antonio de Nebrija, Madrid, Spain
Abstract :
In this paper, a methodology is presented to perform automatic selective TMR insertion on digital circuits, having as a constraint the required reliability level. Such reliability is guaranteed while reducing the area compared with TMR.
Keywords :
circuit complexity; digital circuits; integrated circuit reliability; redundancy; SEU mitigation; automatic insertion; automatic selective TMR insertion; digital circuits; reliability level; Flip-flops; Reliability; Tunneling magnetoresistance; Single Event Upsets (SEUs); Triple Modular Redundancy (TMR); fault injection; optimization;
Conference_Titel :
Radiation and Its Effects on Components and Systems (RADECS), 2008 European Conference on
Conference_Location :
Jyvaskyla
Print_ISBN :
978-1-4577-0481-9
DOI :
10.1109/RADECS.2008.5782728
