• DocumentCode
    3365813
  • Title

    Automatic insertion of selective TMR for SEU mitigation

  • Author

    Ruano, O. ; Reviriego, P. ; Maestro, J.A.

  • Author_Institution
    Univerdad Antonio de Nebrija, Madrid, Spain
  • fYear
    2008
  • fDate
    10-12 Sept. 2008
  • Firstpage
    284
  • Lastpage
    287
  • Abstract
    In this paper, a methodology is presented to perform automatic selective TMR insertion on digital circuits, having as a constraint the required reliability level. Such reliability is guaranteed while reducing the area compared with TMR.
  • Keywords
    circuit complexity; digital circuits; integrated circuit reliability; redundancy; SEU mitigation; automatic insertion; automatic selective TMR insertion; digital circuits; reliability level; Flip-flops; Reliability; Tunneling magnetoresistance; Single Event Upsets (SEUs); Triple Modular Redundancy (TMR); fault injection; optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radiation and Its Effects on Components and Systems (RADECS), 2008 European Conference on
  • Conference_Location
    Jyvaskyla
  • ISSN
    0379-6566
  • Print_ISBN
    978-1-4577-0481-9
  • Type

    conf

  • DOI
    10.1109/RADECS.2008.5782728
  • Filename
    5782728
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3365813