Robust three-state PFD architecture with enhanced frequency acquisition capabilities

The three-state phase-frequency detector (PFD) is commonly used to improve the pull-in range of phase-locked loops, due to its ability to operate also in a frequency discriminator mode. However the delay of the feedback path, needed to eliminate the dead zone problem, limits the speed performance of the circuit and its linear input range, and can lead to average differential outputs with the wrong polarity, which disturb the acquisition process of the PLL. In this paper we present an alternative implementation of a three-state PFD, that with simple hardware modifications solves the problem of output polarity reversal, achieving much better frequency acquisition capabilities. The architecture does not rely on any assumption on the underlying VLSI technology.