Improved Low Power Full Scan BIST

This paper proposes a low power scan-based BIST scheme that can reduce test length and switching activity in CUT without compromising fault coverage. The proposed scheme aims at improving test quality and power dissipation by combining some solutions available in the literature. It combines test-per-clock and test-per-scan test application methods, uses two functional lengths during scan, and a low transition random test pattern generator (LT-RTPG) as TPG. Experimental results on ISCAS89 benchmark circuits demonstrate that the proposed scheme reaches the desired fault coverage with significantly shorter test length while maintaining transition reduction.