A Heuristic Fault Dictionary Reduction Methodology

Author

Pulka, Andrzej

Author_Institution

Silesian Univ. of Technol., Gliwice

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

1115

Lastpage

1118

Abstract

The paper concerns problems of electronic analog devices diagnoses. Various optimization techniques in the field of test point selection are discussed. New proposed modifications and improvements have form of algorithms implemented as an expert system in PROLOG language. The searching procedures are exemplified on benchmark circuits. The problem of extension of the methodology to complex fault dictionaries is considered.

Keywords

analogue circuits; circuit reliability; fault diagnosis; PROLOG language; electronic analog devices diagnoses; fault dictionaries; heuristic fault dictionary reduction; Analog circuits; Circuit faults; Circuit simulation; Circuit testing; Design for testability; Dictionaries; Electronic equipment testing; Fault diagnosis; Process design; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on

Conference_Location

Marrakech

Print_ISBN

978-1-4244-1377-5

Electronic_ISBN

978-1-4244-1378-2

Type

conf

DOI

10.1109/ICECS.2007.4511190

Filename

4511190

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3365922