Non-algorithmic stress optimization using simulation for DRAMs

Author

AL-Ars, Zaid ; Hamdioui, Said

Author_Institution

Lab. of Comput. Eng., Delft Univ. of Technol., Delft, Netherlands

fYear

2009

fDate

15-17 Nov. 2009

Firstpage

1

Lastpage

6

Abstract

Stress optimization for memory devices is a complex process due to the continuous space of possible optimization values for relevant parameters. This paper uses a method based on electrical Spice simulation to perform this optimization process for DRAM devices. The paper presents a case-study performed in Qimonda to optimize the timing and temperature stresses for the strap problem in defective memory cells. The paper also considers the impact of bit line coupling effects on the faulty behavior and identifies the worst case coupling background needed to detect the faulty cells.

Keywords

DRAM chips; SPICE; circuit optimisation; failure analysis; DRAM devices; Qimonda; bit line coupling effects; electrical Spice simulation; faulty cell detection; memory cells; memory devices; nonalgorithmic stress optimization; optimization values; strap problem; Analytical models; Circuit faults; Circuit simulation; Optimization methods; Random access memory; Space technology; Stress; Temperature; Testing; Timing; DRAM testing; Spice simulation; non-algorithmic stresses; strap problem; stress optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test Workshop (IDT), 2009 4th International

Conference_Location

Riyadh

Print_ISBN

978-1-4244-5748-9

Type

conf

DOI

10.1109/IDT.2009.5404373

Filename

5404373