A time-interleaved pipelined ADC chip design for 4-G application

A 10-bit 60-MS/s time-interleaved pipelined analog-to-digital converter (ADC) is successfully designed and implemented in TSMC 0.18 μm CMOS process. The time-interleaved technology is chosen to reduce the opamp´s bandwidth requirement and promote the sampling rate. The proposed ADC adopts opamp sharing technique and SHA-less (Sample Hold Amplifier-less) architecture to lower power consumption. Additional switches are introduced to reduce the crosstalk between the two opamp-sharing successive stages. Measured DNL (differential nonlinearity) and INL (integral nonlinearity) of the proposed ADC are less than 1.28 LSB (least significant bit) and 1.8 LSB, respectively at full sampling rate of 60 MS/s. The ADC exhibits an ENOB of 8.12 bits and consumes power of 30.6mW from 1.8-V power supply. The chip area including pads only occupies 2.46 mm².