Title :
Design of 2Ã\x97VDD-Tolerant I/O Buffer with Considerations of Gate-Oxide Reliability and Hot-Carrier Degradation
Author :
Tsai, Hui-Wen ; Ker, Ming-Dou
Author_Institution :
Nat. Chiao-Tung Univ., Hsinchu
Abstract :
A new 2×VDD-tolerant I/O buffer circuit, realized with only 1×VDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2×VDD-tolerant I/O buffer has been implemented in a 130-nm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the additional thick gate-oxide (2.5-V) devices. This 2×VDD-tolerant I/O buffer has been successfully confirmed by the experimental results with a signal speed of up to 133 MHz for PCI-X application.
Keywords :
CMOS integrated circuits; MOSFET; buffer circuits; hot carriers; integrated circuit design; integrated circuit reliability; nanoelectronics; semiconductor device models; semiconductor device reliability; 2xVDD-tolerant I/O buffer design; gate-oxide reliability; hot-carrier degradation; mixed-voltage interface; nanoscale CMOS transistors; size 130 nm; voltage 1.2 V; voltage 2.5 V; CMOS process; CMOS technology; Circuits; Degradation; Diodes; Energy consumption; Hot carriers; MOSFETs; Transistors; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4511221
