Title :
Efficient and Accurate Models of Output Transition Time in CMOS Logic
Author :
Alioto, Massimo ; Poli, Massimo ; Palumbo, Gaetano
Author_Institution :
Univ. of Siena, Siena
Abstract :
In automated design of Very Large Scale of Integration (VLSI) digital circuits with a standard cell approach, accurate timing analysis is of utmost importance. Due to the strong impact of the input (rise/fall) transition time on the delay of succeeding gates in nanometer technologies, the output transition time of CMOS gates must be modeled with adequate accuracy [1]. In this paper, a simple and an accurate output transition time model based on the approach in [2]-[5] are proposed. Extensive model validation has been made by means of Spectre simulations on a 90 nm technology, which confirm the good accuracy of the models.
Keywords :
CMOS logic circuits; VLSI; CMOS gates; CMOS logic; nanometer technologies; very large scale integration digital circuits; Analytical models; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Delay effects; Digital circuits; Semiconductor device modeling; Timing; Very large scale integration; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location :
Marrakech
Print_ISBN :
978-1-4244-1377-5
Electronic_ISBN :
978-1-4244-1378-2
DOI :
10.1109/ICECS.2007.4511227