DocumentCode
3366596
Title
All-Digital PLL Using Pulse-Based DCO
Author
Huang, Hong-Yi ; Liu, Jen-Chieh ; Cheng, Kuo-Hsing
Author_Institution
Nat. Taipei Univ., Taipei
fYear
2007
fDate
11-14 Dec. 2007
Firstpage
1268
Lastpage
1271
Abstract
A 150-450-MHz, all-digital phase locked-loop (ADPLL) in a 0.18um CMOS process is presented. The pulse-based digitally controlled oscillatr (PB-DCO) performs a high resolution and wide range. The bulk-controlled varactor minimizes jitter performance. The worst case for frequency acquisition is 32 reference clock cycles. The multiplication factor is 2-63. The rms and peak-to-peak jitters are 6.7ps and 44ps at 450-MHz, respectively. Power consumption is 16.2mW at 450-MHz.
Keywords
CMOS digital integrated circuits; digital phase locked loops; jitter; oscillators; varactors; ADPLL; CMOS process; PB-DCO; all-digital phase locked-loop; jitter performance; multiplication factor; power consumption; pulse- based digitally controlled oscillator; varactor; Circuit optimization; Clocks; Delay effects; Digital control; Frequency; Hardware design languages; Jitter; Phase locked loops; Pulse generation; Ring oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Conference_Location
Marrakech
Print_ISBN
978-1-4244-1377-5
Electronic_ISBN
978-1-4244-1378-2
Type
conf
DOI
10.1109/ICECS.2007.4511228
Filename
4511228
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