Title :
IC performance prediction for test cost reduction
Author :
Lee, Jungran ; Walker, D.M.H. ; Milor, Linda ; Peng, Yeng ; Hill, Gene
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
This paper describes a methodology for building models predicting manufactured integrated circuit performances as a function of inline and wafer electrical test measurements. We show how these predictions can be used to predict the performance of an industrial microprocessor, and reduce the average number of speed bins that must be tested by 45%
Keywords :
integrated circuit manufacture; integrated circuit testing; performance evaluation; production testing; IC manufacture; IC performance prediction; industrial microprocessor; speed bins; test cost reduction; wafer electrical test measurements; Circuit testing; Costs; Integrated circuit manufacture; Integrated circuit modeling; Integrated circuit testing; Performance evaluation; Predictive models; Pulp manufacturing; Semiconductor device modeling; Virtual manufacturing;
Conference_Titel :
Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-5403-6
DOI :
10.1109/ISSM.1999.808750
