Feasibility of achieving high calculation speeds on the RASC platform

Author

Wielgosz, Maciej ; Jamro, Ernest ; Wiatr, Kazimierz

Author_Institution

AGH Univ. of Sci. & Technol., Krakow

fYear

2008

fDate

14-17 Sept. 2008

Firstpage

97

Lastpage

100

Abstract

This paper presents results of the tests performed to determine high speed calculations capabilities of the SGI RASC platform. Different data transfer modes and memory management approaches were examined to choose the most effective combination of the Host and RASC memory adjustments. Obtained results of measurements revealed that Direct I/O mode together with DMA transfer provides the highest data throughput between Host and RASC slice. Nevertheless, for some applications multi-buffering may be more suitable in terms of concurrent data transfer and FPGA algorithm execution capability.

Keywords

data communication; field programmable gate arrays; reconfigurable architectures; storage management; DMA transfer; FPGA algorithm execution; RASC memory adjustments; RASC platform; concurrent data transfer; data throughput; data transfer modes; field programmable gate arrays; high speed calculations; memory management; multibuffering; Algorithm design and analysis; Application specific integrated circuits; Bandwidth; Chemistry; Field programmable gate arrays; Hypercubes; Memory management; Testing; Throughput; Topology; FPGA; High Performance Reconfigurable Computing; elementary function; exponent function;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals and Electronic Systems, 2008. ICSES '08. International Conference on

Conference_Location

Krakow

Print_ISBN

978-83-88309-47-2

Electronic_ISBN

978-83-88309-52-6

Type

conf

DOI

10.1109/ICSES.2008.4673367

Filename

4673367