A low-power sample-and-hold circuit based on a switched-opamp technique

Author

Centurelli, Francesco ; Simonetti, Andrea ; Trifiletti, Alessandro

Author_Institution

Dipt. di Ing. Elettron., Univ. di Roma La Sapienza, Roma

fYear

2008

fDate

14-17 Sept. 2008

Firstpage

105

Lastpage

108

Abstract

A novel low-power and high-performance sample-and-hold (S/H) front-end suitable for pipelined and cyclic analog-to-digital converters using 0.25-mum CMOS technology is proposed. This sampler uses a new S/H architecture exploiting a switched telescopic cascode operational transconductance amplifier (OTA) to minimize power consumption. Simulation results show that the proposed solution allows simple and reliable S/H function and an effective power reduction without noise and distortion penalty.

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit reliability; low-power electronics; operational amplifiers; sample and hold circuits; switched networks; CMOS technology; OTA; S/H architecture; cyclic analog-to-digital converter; low-power sample-and-hold circuit; pipelined analog-to-digital converter; power consumption minimization; reliable S/H function; size 0.25 mum; switched telescopic cascode operational transconductance amplifier; switched-opamp technique; CMOS technology; Circuit noise; Circuit simulation; Energy consumption; Power amplifiers; Rails; Space technology; Switches; Switching circuits; Topology; Low power circuits; Sample-and-Hold; Switched-Opamp;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals and Electronic Systems, 2008. ICSES '08. International Conference on

Conference_Location

Krakow

Print_ISBN

978-83-88309-47-2

Electronic_ISBN

978-83-88309-52-6

Type

conf

DOI

10.1109/ICSES.2008.4673369

Filename

4673369