High performance adaptive sensor interface design through model based estimation of analog non-idealities

Accurate and sufficient design of AMS signal paths is always being a challenge for system designers requiring high simulation performance of the analog model which also incorporates circuit level non-idealities. The new SystemC AMS extensions offer high simulation performance as well as capabilities of incorporating circuit level non-ideal effects. In this paper we modelled a low Over Sampling Ratio (OSR), second order Sigma Delta (ΣΔ) Analog to Digital Converter (ADC) which incorporates non-ideal effects like sampling jitter, k_BT/C_S noise, switch non-linearities, band-gap noise and operational amplifier non-idealities (such as finite gain, finite bandwidth, gain nonlinearity, slew rate, leakage and saturation effect). The ADC shows a performance bottle neck of 16 bits. State-of-Art signal conditioning techniques use adaptive correction methods inside the analog part or inside the DSP part of the ADC making it more complicated to realize. In our design we have implemented the adaptive filtration within the micro-controller to correct the noise ground as well as large signal non-linear effects to produce an output which is 20-bits clean, proving sufficiency of low order and low OSR of a ΣΔ ADC for 20 bit resolution as well as a simplified adaptive filtration scheme alleviating the need of adaptive blocks within the ADC.