DocumentCode :
3367185
Title :
Calculation methods of new circuit activity measure for low power modeling
Author :
Brzozowski, Ireneusz ; Kos, Andrzej
Author_Institution :
Dept. of Electron., AGH Univ. of Sci. & Technol., Cracow
fYear :
2008
fDate :
14-17 Sept. 2008
Firstpage :
133
Lastpage :
136
Abstract :
Calculation procedures for the gate driving way probability - the new measure of a circuit activity, developed for low power modeling - are presented in this paper. The new model of power dissipation, using the measure, has improved estimation accuracy. Moreover, it allows developing of new methods for low power design. The gate driving way can be easy calculated using logic simulations, but it is time-consuming method. So, the authors propose efficient and fast calculation procedures. The versatile algorithm for any circuit has been developed as well as very fast one for two-level circuits only. Results of new algorithms using were compared for a set of MCNC benchmark circuits.
Keywords :
CMOS logic circuits; integrated circuit modelling; low-power electronics; probability; MCNC benchmark circuits; circuit activity measure; gate driving way probability; low power modeling; power dissipation; two-level circuits; CMOS logic circuits; Capacitance; Capacitors; Circuit simulation; Clocks; Energy consumption; Frequency; Power dissipation; Power measurement; Semiconductor device modeling; circuit activity; low-power modeling and design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals and Electronic Systems, 2008. ICSES '08. International Conference on
Conference_Location :
Krakow
Print_ISBN :
978-83-88309-47-2
Electronic_ISBN :
978-83-88309-52-6
Type :
conf
DOI :
10.1109/ICSES.2008.4673376
Filename :
4673376
Link To Document :
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