Title :
A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology
Author :
Kopanski, Jakub ; Pleskacz, Witold A. ; Pienkowski, Dariusz
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland
Abstract :
In this paper a 5Gb/s equalizer has been presented. It is designed to operate within USB 3.0 transceiver and compensates for frequency dependent losses introduced by transmission channel. For the reference signal, the clock and data recovery circuit has been used. This approach allowed to minimize the equalizer components. Critical equalizer building blocks have been implemented in GLOBALFOUNDRIES 65 nm Low Power CMOS technology. Other blocks are modeled in hardware description language. Mixed-signal system simulation results show full functionality of the proposed solution.
Keywords :
CMOS integrated circuits; equalisers; low-power electronics; peripheral interfaces; GLOBALFOUNDRIES; USB 3.0 receiver; bit rate 5 Gbit/s; equalizer; frequency dependent losses; hardware description language; low power CMOS technology; mixed-signal system simulation; size 65 nm; transmission channel; CMOS integrated circuits; Clocks; Detectors; Equalizers; Integrated circuit modeling; Receivers; Universal Serial Bus;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location :
Cottbus
Print_ISBN :
978-1-4244-9755-3
DOI :
10.1109/DDECS.2011.5783063
