• DocumentCode
    3367719
  • Title

    Communication modelling and synthesis for NoC-based systems with real-time constraints

  • Author

    Tagel, Mihkel ; Ellervee, Peeter ; Hollstein, Thomas ; Jervan, Gert

  • Author_Institution
    Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
  • fYear
    2011
  • fDate
    13-15 April 2011
  • Firstpage
    237
  • Lastpage
    242
  • Abstract
    This paper addresses the communication modelling and synthesis problem for applications implemented on networks-on-chip. Due to the communication complexity of such systems it is difficult to estimate the communication delay. On the other hand, guaranteeing the timing constraints without detailed know-how about the communication is impossible. In this work we propose a communication modelling and synthesis approach for networks-on-chip where communication infrastructure is not able to provide communication interleaving (such as TDMA, virtual channels) or to guarantee communication delays. The idea is, to design a communication synthesis method, which would not be run off-chip as a CAD tool on a workstation, but on-chip and being activated whenever the system-on-chip (SoC) is re-configured.
  • Keywords
    integrated circuit modelling; network-on-chip; CAD tool; NoC-based systems; communication Modelling; communication delays; communication synthesis method; networks-on-chip; real-time constraints; Complexity theory; Delay; Routing; Schedules; Solid modeling; Switches; System-on-a-chip; Communication modelling; Communication synthesis; Network-on-chip; System-level design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
  • Conference_Location
    Cottbus
  • Print_ISBN
    978-1-4244-9755-3
  • Type

    conf

  • DOI
    10.1109/DDECS.2011.5783086
  • Filename
    5783086