VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders

Author

Wang, Yueh-Yi ; Peng, Yan-Tsung ; Tsai, Chun-Jen

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

In this paper, a new complexity-reduced method and its hardware architecture for motion estimation and the in-loop filter for MPEG-4 AVC/H.264 is proposed. The proposed method is focused on the computation reduction for the motion search algorithm among multiple reference frames and the mode partition determination. Furthermore, to verify the functionality and performance of the proposed hardware design, an emulation board platform, the ARM Integrator, is used for H.264 hardware/software co-development. The experimental results show that the proposed method has excellent performance with little or no degradation of coding efficiency.

Keywords

VLSI; circuit complexity; digital filters; hardware-software codesign; integrated circuit design; motion estimation; video coding; ARM integrator; MPEG-4 AVC/H.264 encoders; VLSI architecture design; coding efficiency; emulation board platform; hardware-software design; in-loop filter; mode partition determination; motion estimator; motion search algorithm; multiple reference frames; Automatic voltage control; Computer architecture; Emulation; Filters; Hardware; MPEG 4 Standard; Motion estimation; Partitioning algorithms; Software performance; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329230

Filename

1329230