A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring

In this paper, we present an adaptive voltage scaling (AVS) scheme to tune the supply voltage of digital circuits according to variations. Compared to worst-case designs, which produce fixed and excessively large safety margins, a considerable amount of energy can be saved by this approach. The AVS technique is based on in-situ delay monitoring, i.e. observing the timing in critical paths. For this task, we propose a Pre-Error flip-flop, that is capable of detecting late data transitions - so-called pre-errors. We provide an in-depth analysis, that is based on a Markov model, to describe the closed loop voltage regulation. We simulated the power saving potential compared to the worst-case design and obtained a reduction of 13.5% in active energy for a negligible error rate of 1E-15. Moreover, we illustrate the opportunity to further reduce the power consumption when tolerating higher error rates. This way, our approach can gain the optimal power saving for a given allowed failure probability.