ESL solutions for low power design

Power consumption has become one of the major concerns in today´s integrated circuit design, and especially in System-on-Chip development where numerous heterogeneous functions are integrated in a single chip. In this context system architects have the challenge to identify power issues very early in the design flow from a complex set of use scenarios. This paper explains how to achieve this challenge through the deployment of a modeling framework that enables low power technique exploration. The principle that sustains the framework is first introduced. A description of some of the power saving techniques that can be supported together with a presentation of the modeling data then follows. A few examples finally show the results a system designer can expect using the framework.