Analysis of abnormal Pch Vt distribution in wafer caused by implanter

Author

Nishimura, Kozo ; Maeda, Tsutomu ; Inoue, Takayoshi ; Suzuki, Tomonari ; Katsumoto, Kenichi

Author_Institution

Integration Eng. Group, KMT Semicond. Ltd., Hyogo, Japan

fYear

1999

fDate

1999

Firstpage

341

Lastpage

344

Abstract

In this paper, we report an analysis in which the abnormal p-channel threshold voltage (Pch Vt) distribution in a wafer was found to be due to the malfunction of an implanter at the Pch Vt adjustment step. The analysis was performed using a pulse C-V method and experiments with production wafers. As the conventional thermal wave and Rs measurements were not sensitive enough for this problem, the methodology of the monitoring method is discussed through our experiences

Keywords

CMOS integrated circuits; MOS integrated circuits; integrated circuit manufacture; ion implantation; process monitoring; voltage distribution; PMOS; abnormal threshold voltage distribution; implanter malfunction; monitoring method; p-channel threshold voltage; production wafer experiments; pulse C-V method; wafer production line; Annealing; Capacitance-voltage characteristics; Electrical resistance measurement; Ion implantation; Large scale integration; Leakage current; Monitoring; Production; Thermal resistance; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on

Conference_Location

Santa Clara, CA

ISSN

1523-553X

Print_ISBN

0-7803-5403-6

Type

conf

DOI

10.1109/ISSM.1999.808806

Filename

808806