A low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter

This work proposes a digital sinc filter based on the direct implementation of the convolution relationship between the input samples and the filter coefficients. The proposed technique is an alternative to standard CIC approach and implies less hardware complexity that translates in power and area savings. The proposed technique has been applied to the design of a complete decimator for a ΣΔ converter intended for cardiac pacemakers. The simulation of a standard cell implementation of the filter proved good functionality of the decimator and demonstrated a 20% power saving for the whole decimator descending from a 50% power saving in the sinc stage.