DocumentCode :
3368404
Title :
Probabilistic equivalence checking based on high-level decision diagrams
Author :
Karputkin, Anton ; Ubar, Raimund ; Tombak, Mati ; Raik, Jaan
Author_Institution :
Tallinn Univ. of Technol., Tallinn, Estonia
fYear :
2011
fDate :
13-15 April 2011
Firstpage :
423
Lastpage :
428
Abstract :
The paper proposes a novel method for probabilistic equivalence checking of digital systems. The method is based on representing the high-level decision diagrams as the model of digital systems by the sets of characteristic polynomials. It is shown that this representation is canonical, i.e. the sets of polynomials for equivalent diagrams are the same up to the names of the variables. However, computing the full set of polynomials is unfeasible for large diagrams as it demands checking all assignments to the control variables. In order to cope with this problem we have developed a polynomial algorithm for probabilistic equivalence checking.
Keywords :
decision diagrams; formal verification; polynomials; characteristic polynomial set; control variable; digital system; equivalent diagram; high-level decision diagram; probabilistic equivalence checking; Boolean functions; Complexity theory; Data structures; Digital systems; Polynomials; Probabilistic logic; Solid modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location :
Cottbus
Print_ISBN :
978-1-4244-9755-3
Type :
conf
DOI :
10.1109/DDECS.2011.5783130
Filename :
5783130
Link To Document :
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