A real-time VLSI median filter employing two-dimensional bit-propagating architecture

A high-speed permutation-network-based VLSI median filter has been developed. By employing a two-dimensional bit-propagating scheme, the delay time of the filter has been made proportional to the sum of the number of inputs and the bit length. As a result, a much faster median search has been achieved compared to conventional approaches, in which the delay time is typically the order of the product of the number of inputs and the bit length. As a proof-of-concept, an 8-b, 5-input median filter chip was designed and fabricated in a 0.35-μm 3-metal CMOS technology. A high-speed median search less than 4.9 ns has been demonstrated by experiments.