DocumentCode
3368911
Title
Design and implementation of a 525 mm2 CMOS digital micromirror device (DMD) display chip
Author
Chiu, Edison H. ; Tran, Can ; Honzawa, Takeshi ; Numaga, Shigeki
Author_Institution
Texas Instrum. Inc., USA
fYear
1995
fDate
31 May-2 Jun 1995
Firstpage
137
Lastpage
139
Abstract
This paper describes a new type of 1280×1024 Digital Micromirror Device (DMD) with 50 MHz serial I/O ports. The DMD uses a unique shadow memory and pixel multiplexing scheme to realize a high-definition television (HDTV) single-chip integrated circuit display device. The project developed defect-tolerant techniques based on memory cell duplication with address decoding to improve the fabrication yield of large-chip-size devices. This DMD chip is fabricated using 0.8 μm single polysilicon and six-level metal CMOS process technology. A unique and optimized pixel with a pixel pitch of 17 μm is obtained as a result of the 25×21 mm2 compact chip design
Keywords
CMOS memory circuits; decoding; electrostatic devices; flat panel displays; high definition television; integrated circuit reliability; micromechanical devices; mirrors; multiplexing; redundancy; television equipment; 0.8 micron; 1024 pixel; 1280 pixel; 50 MHz; HDTV single-chip IC display device; address decoding; defect-tolerant techniques; digital micromirror device display chip; high-definition TV display; memory cell duplication; pixel multiplexing scheme; projection TV; shadow memory; single polysilicon process; six-level metal CMOS process technology; CMOS process; CMOS technology; Decoding; Displays; Fabrication; HDTV; Integrated circuit technology; Integrated circuit yield; Micromirrors; TV;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-2773-X
Type
conf
DOI
10.1109/VTSA.1995.524649
Filename
524649
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