Title :
Features of SOI-LSI for low voltage operation
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan
fDate :
31 May-2 Jun 1995
Abstract :
To reduce the power consumption of electronic devices, using a low supply voltage is very effective although suffering lowered operation speed. One of the solutions to overcome this tradeoff is the SOI-LSI, of which features such as small parasitic capacitance and small substrate bias effect can give high speed operation and small power consumption
Keywords :
MOS integrated circuits; capacitance; integrated circuit technology; integrated circuit testing; large scale integration; silicon-on-insulator; SOI-LSI technology; low voltage operation; operation speed; parasitic capacitance; power consumption; substrate bias effect; Capacitance; Circuits; Delay effects; Energy consumption; Equations; Leakage current; Low voltage; MOSFETs; Optical arrays; Threshold voltage;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2773-X
DOI :
10.1109/VTSA.1995.524650
