A low latency and low power dynamic Carry Save Adder

Author

Datta, Ramyanshu ; Abraham, Jacob A. ; Montoye, Robert ; Belluomini, Wendy ; Ngo, Hung ; McDowell, Chandler ; Kuang, JB ; Nowka, Kevin

Author_Institution

Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

This paper presents a 4-to-2 Carry Save Adder (CSA) using dynamic logic and the Limited Switch Dynamic Logic (LSDL) circuit family. Adders are a crucial portion of all floating-point units, since they form the base element of all arithmetic functions. The 4-to-2 circuits reported previously do not meet the requirements of the next generation of processors. The adder presented here is built using a dynamic circuit style that improves performance significantly. Further a latching element after each dynamic evaluation node controls the power of the dynamic circuits. In this paper we project some of the salient features of the LSDL circuit family by comparing this 4-2 circuit with the most similar static implementation. Use of the LSDL circuit family displays significant improvement not only in terms of performance but also with respect to power dissipation, leakage and area.

Keywords

adders; carry logic; flip-flops; leakage currents; logic circuits; arithmetic functions; dynamic evaluation node controls; latching element; leakage current; leakage sensitivity; limited switch dynamic logic circuit family; low latency; low power dynamic carry save adder; power dissipation; static implementation; switching dynamic logic circuit; transistor width; Adders; Compressors; Delay; Jacobian matrices; Logic circuits; Logic gates; Multiplexing; Power engineering computing; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329312

Filename

1329312