A new method and the realization of error code testing

Bit synchronization and sequence synchronization are two crucial technologies in error code tester. In traditional error code tester, digital PLL method applied in bit synchronization and sequence synchronization realized through the sequence´s correlation, resulted in a low speed on bit and sequence synchronization. This paper came up with new methods to realize bit and sequence synchronization, which were Code-edge-catching method and Injecting-receiving sequence method. FPGA was applied to achieve all function modules of tester. The debug and simulation results display the time to realize bit synchronization is less than 3/8 of the code cycle. There is only a m sequence´s cycle to realize sequence synchronization. This new CER tester has many advantages, such as eliminating false sequence synchronization, bit and sequence synchronization time to be short, and a good hardware synergy.