A programmable processor with multiple functional units and banked registers for general purpose numerical processing

Author

Morifuji, Takafumi ; Takeuchi, Yoshinori ; Imai, Masaharu

Author_Institution

Dept. of Inf. & Math. Sci., Osaka Univ., Japan

Volume

4

fYear

1999

fDate

15-19 Mar 1999

Firstpage

1985

Abstract

We present an architecture of a general purpose numerical processor (GPNP). The processor with this architecture is capable of running a wide variety of numerical processing and digital signal processing with its programmability. Flexibility and high-performance are achieved by multiple functional units and their data transfer parallelism. The prototype of a GPNP with five functional units can operate with a 33-MHz clock frequency by simulation and its size corresponds with 230-kTr and 34.5-kbytes on-chip memory

Keywords

CMOS digital integrated circuits; digital arithmetic; digital signal processing chips; parallel architectures; programmable circuits; 0.6 micron; 33 MHz; 34.5 kbyte; CMOS; DCT; DSP chip; banked registers; clock frequency; digital signal processing; general purpose numerical processor; high-performance; matrix operations; multiple functional units; on-chip memory; parallel data transfer; processor architecture; programmable processor; simulation; Clocks; Digital filters; Digital signal processing; Discrete cosine transforms; Finite impulse response filter; Image coding; Prototypes; Registers; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1999. Proceedings., 1999 IEEE International Conference on

Conference_Location

Phoenix, AZ

ISSN

1520-6149

Print_ISBN

0-7803-5041-3

Type

conf

DOI

10.1109/ICASSP.1999.758316

Filename

758316