Title :
Parallel Turbo decoding
Author :
Zhang, Yuping ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., MN, USA
Abstract :
Turbo codes are one of the most powerful error correcting codes. The VLSI implementation of Turbo codes for higher decoding speed requires use of parallel architectures. This paper explores the design spaces of both serial and parallel MAP decoders using graphical analysis. Several existing designs are compared, and three new parallel decoding schemes are presented.
Keywords :
VLSI; error correction codes; iterative decoding; maximum likelihood decoding; parallel architectures; turbo codes; VLSI implementation; decoding speed; error correcting codes; graphical analysis; parallel MAP decoders; parallel architectures; parallel decoding; parallel turbo decoding; serial MAP decoders; very large scale integrated circuit implementation; Communication system control; Convolutional codes; Error correction codes; Interleaved codes; Iterative decoding; Parallel architectures; Partitioning algorithms; Space exploration; Turbo codes; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1329320
