DocumentCode :
3369388
Title :
A network-flow based pin-count aware routing algorithm for broadcast electrode-addressing EWOD chips
Author :
Huang, Tsung-Wei ; Yeh, Shih-Yuan ; Ho, Tsung-Yi
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear :
2010
fDate :
7-11 Nov. 2010
Firstpage :
425
Lastpage :
431
Abstract :
Electrowetting-on-dielectric (EWOD) chips have emerged as the most widely used actuators for digital microfluidic (DMF) systems. These devices enable the electrical manipulation of microfluidics with various advantages such as low power consumption, flexibility, accuracy, and efficiency. In addressing the need for low-cost and practical fabrication, pin-count reduction has become a key problem to the large-scale integration of EWOD-chip designs. One of the major approaches, broadcast addressing, reduces the pin count by assigning a single control pin to multiple electrodes with mutually compatible control signals. Most previous studies utilize this addressing scheme by scheduling fluidic-level synthesis on pin-constrained chip arrays. However, the associated interconnect routing problem is still not provided in currently available DMF automations, and thus the broadcast-addressing scheme cannot be actually realized. In this paper, we present the first network-flow based pin-count aware routing algorithm for EWOD-chip designs with a broadcast electrode-addressing scheme. Our algorithm simultaneously takes pin-count reduction and wirelength minimization into consideration for higher integration and better design performance. Experimental results show the effectiveness and scalability of our algorithm on a set of real-life chip applications.
Keywords :
integrated circuit interconnections; lab-on-a-chip; large scale integration; low-power electronics; microfluidics; network routing; broadcast electrode-addressing EWOD chips; digital microfluidic systems; electrowetting-on-dielectric chips; fluidic-level synthesis; interconnect routing; large-scale integration; low power consumption; multiple electrodes; mutually compatible control signals; network-flow based pin-count aware routing algorithm; pin-constrained chip arrays; pin-count reduction; real-life chip applications; wirelength minimization; Algorithm design and analysis; Chip scale packaging; Electrodes; Fabrication; Pins; Routing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
978-1-4244-8193-4
Type :
conf
DOI :
10.1109/ICCAD.2010.5653715
Filename :
5653715
Link To Document :
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