A new interpolated symbol timing recovery method

Digital interpolation has been used for symbol timing synchronization in communication systems and magnetic channel read-out. Multiplierless up-sampling is proposed here to mitigate the problem of performance/complexity trade-offs in traditional implementations. The new interpolation architecture results in a small-area, low-power realization and also provides better performance than traditional approaches. Prototype chips with BIST have been fabricated in TSMC 0.25-μm CMOS. These chips have been tested to be fully functional and can run at a clock frequency of 400 MHz.