Title :
IEEE International symposium on performance analysis of systems and software
Abstract :
The following topics are dealt with: differentiating the roles of IR measurement and simulation for power and temperature-aware design; user- and process-driven dynamic voltage and frequency scaling; accuracy of performance counter measurements; GARNET: a detailed on-chip network model inside a full-system simulator; Cetra: a trace and analysis framework for the evaluation of Cell BE; Zesto: a cycle-level simulator for highly detailed microarchitecture exploration; Lonestar: a suite of parallel irregular program; exploring speculative parallelism in SPEC2006; machine learning based online performance prediction for runtime parallelization and task scheduling; WARP: enabling fast CPU scheduler development and evaluation; CMPSchedSim: evaluating OS/CMP interaction on shared cache management; understanding the cost of thread migration for multi-threaded Java applications running on a multicore platform; the data-centricity of Web 2.0 workloads and its impact on server performance; characterizing and optimizing the memory footprint of De Novo Short Read DNA sequence assembly; analytic model of optimistic software transactional memory; analyzing CUDA workloads using a detailed GPU simulator; evaluating GPUs for network packet signature matching; online compression of cache-filtered address traces; analysis of the TRIPS prototype block predictor; experiment flows and microbenchmarks for reverse engineering of branch predictor structures; analyzing the impact of on-chip network traffic on program phases for CMPs; SuiteSpecks and SuiteSpots: a methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code; accurately approximating superscalar processor performance from traces; and QUICK: a flexible full-system functional model.
Keywords :
Internet; Java; benchmark testing; coprocessors; electric potential; learning (artificial intelligence); multi-threading; multiprocessing systems; performance evaluation; reverse engineering; scheduling; simulation; storage management; CMPSchedSim; Cell BE; Cetra; De Novo Short Read DNA sequence assembly; GARNET; GPU simulator; Lonestar; SuiteSpecks; SuiteSpots; TRIPS prototype block predictor; WARP; Web 2.0; Zesto; assembly code; benchmarking programs; branch predictor structures; cache-filtered address traces; cycle-level simulator; data centricity; fast CPU scheduler development; flexible full-system functional model; frequency scaling; full-system simulator; machine learning; memory footprint; microarchitecture exploration; multi-threaded Java application; multicore platform; network packet signature matching; on-chip network model; on-chip network traffic; online compression; online performance prediction; optimistic software transactional memory; performance counter measurements; power-aware design; process-driven dynamic voltage; reverse engineering; runtime parallelization; server performance; shared cache management; superscalar processor performance; task scheduling; temperature-aware design; trace and analysis framework;
Conference_Titel :
Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
978-1-4244-4184-6
DOI :
10.1109/ISPASS.2009.4919624
