Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-μm CMOS technology

Author

Chuang, Che-Hao ; Ker, Ming-Dou

Author_Institution

Product & ESD Eng. Dept., Ind. Technol. Res. Inst., Hsinchu, Taiwan

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

This paper presents a 1.2 V/2.5 V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixed-voltage I/O interfaces. The new proposed 1.2 V/2.5 V tolerant I/O buffer design has been successfully verified in a 0.13-μm salicided CMOS process, which can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.

Keywords

CMOS integrated circuits; buffer circuits; electrostatic discharge; integrated circuit design; leakage currents; 0.13 micron; 1.2 V; 2.5 V; CMOS technology; electrostatic discharge; floating N-well circuits; gate tracking circuits; leakage current; mixed voltage tolerant I/O interface design; thin gate oxide devices; tolerant I/O buffer design; CMOS process; CMOS technology; Circuits; Degradation; Electrostatic discharge; Leakage current; MOS devices; Nanoelectronics; Power supplies; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329337

Filename

1329337