Title :
Smart stackingTM technology: An industrial solution for 3D layer stacking
Author :
Blanchard, C. Lagahe ; Radu, I. ; Sadaka, M. ; Landry, K.
Author_Institution :
SOITEC, Crolles, France
Abstract :
Smart Stacking™ is a wafer-to-wafer stacking technology of partially or fully processed wafers. This technology enables transferring very thin layers in a high volume manufacturing environment. The core technologies are surface conditioning, low temperature direct bonding and wafer thinning (figure 1). This technology is adapted for advanced semiconductor applications such as Back Side Illumination (BSI) CMOS Image Sensors (CIS) as well as 3D integration approaches.
Keywords :
CMOS image sensors; stacking; three-dimensional integrated circuits; 3D integration; 3D layer stacking; Smart Stacking technology; back side illumination CMOS image sensors; fully processed wafer; high volume manufacturing environment; partially processed wafer; semiconductor applications; wafer thinning; wafer-to-wafer stacking technology; Bonding; Stacking; Surface morphology; Surface topography; Surface treatment; Three dimensional displays;
Conference_Titel :
IC Design & Technology (ICICDT), 2011 IEEE International Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4244-9019-6
DOI :
10.1109/ICICDT.2011.5783202