Leakage power reduction for clock gating scheme on PD-SOI

This paper presents a technique for reducing leakage power of the circuits employing a clock gating scheme on Partially Depleted Silicon On Insulator (PD-SOI). To reduce leakage power while a local clock is disabled, V_th of each transistor is dynamically controlled by body biasing corresponding to the mode of the local clock. Using PD-SOI is the key to control V_th within one clock cycle by forward biasing, where V_th without biasing is designed higher than usual to reduce leakage power. The SPICE simulation results have shown that the proposed technique reduces leakage power by 82% with small area penalty.