Implementation of MCML universal logic gate for 10 GHz-range in 0.13 μm CMOS technology

Author

Khabiri, Shahnam ; Shams, Maitham

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

In this work¹ an optimization method for designing the universal MOS Current Mode Logic (MCML) gate for high-speed applications is developed. The optimization method is then applied to the standard and two modified topologies of the universal logic gate that are proposed in this article. The target frequency of operation is 10 GHz and above. The reported results are compared in terms of speed, area, and power dissipation. The modified topologies improve the speed by 25% to 30% over that of the standard topology, while dissipating the same amount of power. All simulations are done in a 0.13 μm standard CMOS process, using Spectre simulator.

Keywords

CMOS logic circuits; current-mode logic; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; logic design; logic gates; logic simulation; network topology; 0.13 micron; 10 GHz; CMOS technology; MCML universal logic gate; MOS Current Mode Logic gate; Spectre simulator; circuit topology; high speed integrated circuit; integrated circuit design; integrated circuit modelling; power dissipation; standard CMOS process; CMOS logic circuits; CMOS process; CMOS technology; Design methodology; Frequency; Logic design; Logic gates; Optimization methods; Power dissipation; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329356

Filename

1329356