Contention reduced/conditional discharge flip-flops for level conversion in CVS systems

Clustered Voltage Scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the efficient level converter with fewer overheads in power and delay. Several novel level conversion flip-flops (LCFF) are proposed: a single-ended contention reduced LCFF (CR-LCFF) and double-ended conditional discharge LCFFs (CD-LCFF). Novel circuit techniques are employed for reducing the LCFF overhead, including conditional discharge technique which effectively suppresses dynamic power, contention reduce technique which suppresses short circuit power in DCVSL circuits during transition. A new pulse generator with 10 transistors is used in the proposed LCFFs. In view of PDP, the new LCFFs outperform previous published designs by about 37.7%-41%.