DocumentCode
3370162
Title
SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code
Author
Ringenberg, Jeff ; Mudge, Trevor
fYear
2009
fDate
26-28 April 2009
Firstpage
227
Lastpage
237
Abstract
This paper introduces a methodology to reduce the overall simulation time of large benchmarking suites. Previous work shows that it is possible to simulate only small sections of a benchmark´s dynamic instruction stream in detail without sacrificing accuracy in simulation results with respect to overall behavior. As benchmarking suites increase in size, many such techniques still require a great deal of simulation time to complete. The methods presented in this paper build on this previous work by converting representative sections of a benchmark´s execution into intrinsically checkpointed assembly (ITCY) code that can serve as a replacement for the original benchmark. In addition, a methodology is proposed that creates new benchmark binaries that no longer need input files or system calls in order to execute properly. Simulations of the new benchmarks are much faster, require less overhead, and still properly represent the original benchmark´s execution profile. Results show that benchmarks created using these techniques can be very portable and accurately predict the performance of the original benchmark. An average error rate of less than 5% is achieved when compared to the original representative sections. In addition, a speedup of approximately 60times per benchmark is achieved over a standard set of SimPoints when the new benchmarks are executed serially and 1000times when executed in parallel. This translates into a reduction in simulation time from months to minutes and greatly decreases the amount of time necessary to test a new design.
Keywords
checkpointing; program assemblers; SuiteSpecks; SuiteSpots; intrinsically checkpointed assembly code; Assembly; Benchmark testing; Checkpointing; Computational modeling; Computer science; Computer simulation; Error analysis; Microarchitecture; Microprocessors; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on
Conference_Location
Boston, MA
Print_ISBN
978-1-4244-4184-6
Type
conf
DOI
10.1109/ISPASS.2009.4919654
Filename
4919654
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