Title :
Beta-Matrix ESD network: Throughout end of placement rules?
Author :
Bourgeat, J. ; Galy, P. ; Jacquier, B.
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
Electrostatic Discharge (ESD) protection for advanced CMOS technologies is based on efficient device Network. But these protection strategies imply some constraint on IO and particularly on the frame and the placement in IO ring. In this context we develop and propose an ESD network with Beta-Matrix power device and its own trigger circuit which are integrated in each IO. We obtain a new local strategy which allows removing all IO placement constraint.
Keywords :
CMOS integrated circuits; electrostatic discharge; trigger circuits; ESD protection; IO placement constraint; advanced CMOS technology; beta-matrix ESD network; beta-matrix power device; device network; electrostatic discharge; placement rule; trigger circuit; Clamps; Electrostatic discharge; Logic gates; Qualifications; Rails; Thyristors; Trigger circuits; Beta-Matrix; ESD; ESD network; SCR;
Conference_Titel :
IC Design & Technology (ICICDT), 2011 IEEE International Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4244-9019-6
DOI :
10.1109/ICICDT.2011.5783235
