Title :
Comparative analysis of flip-flop designs for soft errors at advanced technology nodes
Author :
Bhuva, B.L. ; Lilja, K. ; Holts, J. ; Wen, S.-J. ; Wong, R. ; Jagannathan, S. ; Loveless, T.D. ; McCurdy, M. ; Diggins, Z.J.
Author_Institution :
Vanderbilt Univ., Nashville, TN, USA
Abstract :
For advanced fabrication technology nodes, novel single-event related failures are being observed. This paper details efforts to use 3D TCAD simulations to model these failure mechanisms and develop mitigation techniques for flip-flop designs. Simulation, as well as experimental, results are used to show validity of such an approach for future CMOS technologies.
Keywords :
CMOS logic circuits; flip-flops; integrated circuit design; integrated circuit reliability; radiation hardening (electronics); 3D TCAD simulation; CMOS technology; advanced technology node; fabrication technology node; failure mechanisms; flip-flop design; single event related failure; soft error; Flip-flops; Integrated circuit modeling; Layout; Neutrons; Semiconductor process modeling; Solid modeling; Three dimensional displays; CMOS; TCAD simulations; flip-flop; scaling; single-event upsets;
Conference_Titel :
IC Design & Technology (ICICDT), 2011 IEEE International Conference on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4244-9019-6
DOI :
10.1109/ICICDT.2011.5783239
