Gigahertz-range MCML multiplier architectures

Author

Srinivasan, Venkat ; Ha, Dong Sam ; Sulistyo, Jos B.

Author_Institution

Bradley Dept. of Electr. & Comput. Eng., Virginia Tech. VLSI for Telecommun. Lab., Blacksburg, VA, USA

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

In this paper, we present three digital multiplier architectures capable of operating in the gigahertz range, based on MOS Current Mode Logic (MCML) style. A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, (3×2) counter (full adder), [4:2] compressor, and master-slave flip-flop were designed and optimized for high-speed operation. Using these gates, we propose three different 8-bit MCML binary-tree multiplier architectures and compare their performance in terms of latency, throughput (number of multiplications per second) and power consumption. According to our simulation, the fastest multiplier targeting for TSMC 0.18 μm CMOS technology attains a throughput of 4.76 GHz or 4.76 Billion multiplications per second and a latency of 3.8 ns.

Keywords

CMOS logic circuits; adders; compressors; flip-flops; logic design; logic gates; multiplying circuits; power consumption; 0.18 micron; 3.8 ns; 4.76 GHz; CMOS technology; MCML logic gates; MOS Current Mode Logic; NAND/AND; XOR/XNOR; binary-tree multiplier; compressor; counter; full adder; gigahertz range MCML multiplier architecture; master-slave flip-flop; power consumption; Adders; CMOS technology; Counting circuits; Delay; Flip-flops; Logic design; Logic gates; Master-slave; Software libraries; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329389

Filename

1329389