DocumentCode :
3370745
Title :
Internode: internal node logic computational model
Author :
Millan, Alejandro ; Bellido, Manuel J. ; Juan, Jorge ; Guerrero, David ; Ruiz-de-Clavijo, Paulino ; Ostua, Enrique
Author_Institution :
Departamento de Tecnologia Electronica, Univ. de Sevilla, Spain
fYear :
2003
fDate :
30 March-2 April 2003
Firstpage :
241
Lastpage :
248
Abstract :
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal states the gate can reach. This computational model can be used in logic-level tools and is valid for any dynamic behavioral model (delay models, power models, switching noise models, etc.). Also, we show a very efficient implementation of the model, in C language, for N-inputs SCMOS NOR/NAND gates. Finally, we demonstrate the functionality of the model showing three different examples of modeling: (a) a propagation delay model, (b) the degradation delay model (DDM), and (c) a simple power model.
Keywords :
logic CAD; logic gates; logic simulation; C language; Internal Node Logic Computational Model; Internode; computational behavioral model; degradation delay model; dynamic behavioral model; logic gates; logic level tools; Automata; Computational modeling; Degradation; Distributed decision making; Energy consumption; Integrated circuit technology; Logic gates; Power system modeling; Propagation delay;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Simulation Symposium, 2003. 36th Annual
ISSN :
1080-241X
Print_ISBN :
0-7695-1911-3
Type :
conf
DOI :
10.1109/SIMSYM.2003.1192819
Filename :
1192819
Link To Document :
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