Title :
Shared memory systems on the Futurebus
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
fDate :
Feb. 29 1988-March 3 1988
Abstract :
The use of a cache memory on the Futurebus is discussed. An explanation of how these memories work and of cache coherence is given. The MOESI model of cache data is examined. A system of Futurebus modules interacting in the sharing of a single cache line is investigated.<>
Keywords :
buffer storage; computer interfaces; multiprocessing systems; parallel architectures; Futurebus; MOESI model; cache coherence; cache data; cache memory; shared memory systems; Backplanes; Bandwidth; Cache memory; Data structures; Engines; Filters; Memory architecture; Message passing; Microprocessors; System buses;
Conference_Titel :
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-0828-5
DOI :
10.1109/CMPCON.1988.4920
