An architecture for fractal image compression using quad-tree multiresolution

Author

Ramírez, A. Martínez ; Sánchez, A. Díaz ; Aranda, M. Linares ; Pineda, J. Vega

Author_Institution

Instituto Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

Nowadays the fractal image compression is realized by several methods, which are mainly focused to reduce the required number of operations. The present work describes a new architecture to realize fractal image compression. The architecture was designed to be used with a method based on a block classification scheme, using a quad-tree partition on multiple levels of resolution. The simplicity and regularity of the architecture and the method make them adequate to be implemented in programmable logical devices such as FPGAs, or in custom integrated VLSI circuits.

Keywords

application specific integrated circuits; field programmable gate arrays; fractals; image coding; quadtrees; FPGA; block classification scheme; custom integrated VLSI circuits; fractal image compression; programmable logical devices; quad tree multiresolution; quad tree partition; Acceleration; Circuits; Computer architecture; Field programmable gate arrays; Focusing; Fractals; Image coding; Image resolution; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329417

Filename

1329417