Title :
Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies
Author :
Nomura, Kumiko ; Abe, Keiko ; Fujita, Shinobu ; Kurosawa, Yasuhiko ; Kageshima, Atsushi
Author_Institution :
Corp. R&D Center, Toshiba Corp., Japan
fDate :
May 30 2010-June 2 2010
Abstract :
Three-dimensional integrated circuits (3D-IC) have the potential to reduce interconnect length and improve performance especially in sub-65nm CMOS technologies. This paper describes design and performance analysis of the 3D-IC in sub-65nm CMOS technologies based on the accurate calculation of interconnects delays using 16-core processors as case studies. Performance improvement of the 3D-IC vs. 2D-IC is increased as CMOS scales down, which is consistent with the expected trend. The performance improvement is over 20%. Furthermore, performance of the 3D-IC in 65 nm (or 45 nm) CMOS technology is superior to that of the 2D-IC in 45 nm (or 32 nm) CMOS technology. It indicates that design conversion from 2D-IC to 3D-IC is superior to the CMOS technology migration according to COMS scaling. Reduction in repeater buffers and area overhead is also estimated.
Keywords :
CMOS integrated circuits; integrated circuit design; multiprocessing systems; performance evaluation; three-dimensional integrated circuits; 3D-IC; CMOS technology; interconnect delay; multicore processor; performance analysis; size 65 nm; three dimensional integrated circuit; CMOS process; CMOS technology; Delay; Integrated circuit interconnections; Integrated circuit technology; Large scale integration; Multicore processing; Performance analysis; Three-dimensional integrated circuits; Through-silicon vias;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5536963
