Combining circuit and packet switching with bus architecture in a NoC for real-time applications

Real-Time applications generate both streaming and best-effort traffics. The on-chip interconnection network for these applications must be able to guarantee Quality of Service "QoS" for streaming traffic and no packet loss for best-effort traffic. In order to efficiently handle both streaming and best-effort traffic, we propose in this paper a hybrid network on chip architecture, which combines CDMA-based circuit switching, packet switching and CDMA-based bus. We show that with the proposed architecture, bounds on latency and throughput can be configurable according to application constraints, thereby meeting QoS requirements in a hybrid traffic environment.